This application claims benefit of priority under 35 USC xc2xa7119 to Japanese Patent Application No. 2001-091296 filed on Mar. 27, 2001, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory such as a static random access memory, and more particularly relates to a semiconductor memory implemented with a test circuit and a method of testing a semiconductor memory.
2. Description of Related Art
In recent years, the increases in the storage capacity and improvements in the power saving structure on the standby mode of semiconductor memories such as the static random access memory have been advanced. The frequency of occurrence of defective bit locations tends to increase as the storage capacity increases, so that, in the test process, defective memory cells are replaced by redundancy memory cells in accordance with the redundancy circuitry technique in order to relieve malfunctions resulting from defective bits.
It is sometimes the case, however, that there is a memory cell(s) through which current leakage exceeding an allowable value passes, while the static random access memory including the defective memory cell can be normally operated without a problematic function. If there is such a memory cell, however, the consumption current of the standby mode increases.
Therefore, the semiconductor memory including a test circuit which tests to detect the location of a memory cell through which a leakage current is flowing has been proposed. Then, a laser fuse connecting the detected memory cell and electric power source terminals is fused and disconnected in order to interrupt the leakage current path, then the defective memory is replaced by a redundancy cell.
However, the conventional semiconductor memory including the test circuit has the following problem.
When measuring a leakage current value, a long time is needed in order to set the initial value to a desired value of static memory cell data in particular in a static memory cell consisting of flip-flop. As a result, in the case of recent semiconductor memories of large capacity, there is the problem that test time becomes enormous.
A semiconductor memory in one embodiment according to the present invention includes a group of memory cells arrayed in a matrix, memory cell electric power source lines configured to connect the respective memory cells arrayed in a direction of rows of the group of memory cells of each of the rows, two electric power source terminals configured to be mutually independent, and switches configured to be connected between the memory cell electric power source lines and the two electric power source terminals respectively, to be controlled to turn ON/OFF by a inversion logic operation based on a test mode switching signal for switching to and from a test mode and a normal operation mode, and to connect the memory cell power source line to either of the two electric power source terminals according to the ON/OFF control.
In addition, a semiconductor memory in another embodiment according to the present invention includes a memory cell array in which memory cells are arrayed in a matrix, a plurality of word lines provided within the memory cell array, each of the word lines connected to a same number of the memory cells in a row direction, a word line selection circuit including an input terminal connected to a row selection line for selecting a row and configured to select a predetermined word line among from the plurality of word lines, a plurality of memory cell electric power source lines arrayed in the row direction of the memory cell array, a row decoder configured to output a selection signal for selecting the row selection line based on a row addressing signal, first and second electric power source terminals configured to be mutually independent, and electric power source switching circuits respectively provided to either end of the memory cell electric power source lines and configured to supply electric power from the first electric power source terminal to the memory cells of the rows to be tested and to supply electric power from the second electric power source terminal to the memory cells except the memory cells of the rows to be tested in the test mode.
Furthermore, a method of testing a semiconductor memory in one embodiment according to the present invention includes, sequentially selecting memory cell electric power source lines of rows to be tested from a plurality of memory cell electric power source lines arrayed in the row direction of a memory cell array in which memory cells are arrayed in a matrix, supplying leak testing electric power from a first electric power source terminal to the memory cells of the selected rows to be tested and supplying electric power from a second electric power line to the memory cells of the rows except the rows to be tested, and measuring a leakage current value of the rows to be tested in order to detect a row including a memory cell where the leakage current is occurring.